1. Technical Field
The present invention generally relates to an apparatus and method for controlling a level 0 cache and, more particularly, to an apparatus and method for controlling a level 0 cache in order to prevent a fault caused by a soft error.
2. Description of the Related Art
Generally, a cache is located between a processor and main memory. A cache enables faster responses than main memory, which has a low access speed in comparison to the fast processing speed of a processor, and is memory that has a smaller capacity than main memory.
A cache temporarily stores instructions and data, required by a processor, along with the addresses thereof. When external factors cause an error in the cache, the processor may read the wrong instruction from the cache and consequently perform an unwanted operation, or may not interpret the instruction (in other words, the instruction may be a non-existent instruction). Also, when an error occurs in the cache due to external factors, incorrect data may be read from the cache, and a program executed by the processor may output a result that differs from the expected result. Therefore, when external factors cause an error in a processor and a cache, it is necessary to correct the error in order to prevent a fault.
As a related art pertaining to the present invention, there are US Patent No. 2014-0223102, titled “Flush control apparatus, flush control method and cache memory apparatus”, US Patent No. 2014-0095794, titled “Apparatus and method for reducing the flushing time of a cache”, and US Patent No. 2012-0042126, titled “Method for concurrent flush of L1 and L2 caches”.